2.2 \u2013 Pentium 4<\/h4>\n
The Pentium4 is based upon Intel’s 0.13 m and 0.18 m fabricated manufacturing process, offering clock speeds from 1.80 GHz to 2.80 GHz and 1.70 GHz to 1.90 GHz respectively. And is fully compatible with existing Intel\u00ae Architecture-based software.<\/p>\n
The Pentium 4 is a 32-bit RISC processor and has a number of new features that Intel claim will advance performance over previous architectures. These new features marketed as the NetBurst\u00e4 micro-architecture include an Execution Trace Cache, which is way to implement the level 1 instruction cache. It caches the decoded instructions thus removing the latency associated with the instruction decoder from the main execution loops. The processor has an enhanced floating-point and multimedia unit and a \u2018hyper pipelined technology\u2019. The hyper-pipelined technology basically doubles the pipeline depth found in the Pentium 3 from 10 stages to 20.<\/p>\n
Other features include two Arithmetic Logic Units (ALUs), which are clocked at twice the core processor frequency and 128-bit floating-point registers. It also includes an enhanced branch prediction algorithm that has the net effect of reducing the number of branch miss-predictions by about 33% over the P6 generation processor’s branch prediction capability.<\/p>\n
- \n
- 20 stage \u2018hyper pipelined\u2019 technology.<\/li>\n
- 128-bit floating-point registers.<\/li>\n
- Execution Trace Cache.<\/li>\n
- 400 MHz system bus.<\/li>\n<\/ul>\n
3.0 \u2013 Instruction Set Architecture<\/h3>\n
3.1 \u2013 UltraSparc III Cu<\/h4>\n
A fundamental feature of the UltraSparc III core is Instruction Level Parallelism (ILP). ILP allows multiple non-dependent operations to be executed simultaneously. Since the UltraSparc III contains independent execution units for operations such as MOV (transfer instruction) and SUB (Integer Execution Instruction), several instructions can be executed concurrently. With this parallel execution technique, a programmer can achieve true ILP. Another feature of the V9 ISA is that there are data pre-fetch instructions. These instructions allow software to give warning to hardware that it will be using data in the future.<\/p>\n
An addition to the V9 architecture are the Visual Instruction Set (VIS) which uses a series of specialized commands to complete normally CPU intensive graphic operations. VIS addresses performance concerns by dividing standard floating-point graphic operations across the entire scope of the integer and floating-point execution units. VIS operations rely on integer registers for loading and storing data, while floating-point registers provide power for data manipulation.<\/p>\n
![\"floating](\"\/media\/images\/blog\/floating-point.jpg\")
<\/p>\nFigure 1. The floating-point unit supports five different functions including two specifically tailored for graphics (courtesy of http:\/\/sunsite.ics.forth.gr)<\/p>\n
<\/p>\n
An UltraSPARC III Cu processor contains 160 general-purpose 64-bit r registers. The registers in the floating-point register set (also used for VIS and block load store instructions) are combined in specific ways to support data sizes up to 128 bits. All integer registers and the upper floating-point registers are 64 bits wide.<\/p>\n
3.2 – Pentium 4<\/h4>\n
IA32 is the name used by Intel to describe their 32-bit instruction set architecture. The Intel NetBurst micro-architecture supports the entire IA32 instruction set including Intel’s MMX™ technology and the Streaming SIMD (Single Instruction Multiple Data) Extension.<\/p>\n
An additional 144 instructions called the Streaming SIMD Extensions 2 or SSE2 have been added that compliment MMX technology and SSE instructions by supplying increased computation capability, support for larger data types (e.g. double precision floating point numbers and 64-bit packed integer numbers), new cache and memory management instructions and several data handling and conversion instructions. In addition to these, the Pentium4 has enhanced its floating-point unit from its predecessors P6 architecture.<\/p>\n
- \n
- 8 general-purpose registers, 32-bit<\/li>\n
- 6 segment registers, 16-bit<\/li>\n
- 8 floating-point and 8 MMX registers, 64- bit<\/li>\n
- 8 XMM registers for SSE operations, 128-bit<\/li>\n<\/ul>\n
![\"architectural](\"\/media\/images\/blog\/arch-block-digram.jpg\")
<\/p>\nFigure 2. Pentium 4 Architectural diagram. (Courtesy of www.tomshardware.com)<\/p>\n
3.3 – Comparison<\/h4>\n
The first obvious difference between the two processors is the mammoth divide in clock speeds, with the P4 (Pentium 4) offering up to 2.8GHz and the U3 (UltraSParc III) offering up to 1050 MHz. Although I will tackle this later on, the difference in speed is does not offer a linear-increase in performance. The second obvious difference is the 32-bit and 64-bit architecture from the P4 and U3 respectively. 32-bit operations can affect calculations, memory capacity, and storage access. Although the P4 has implemented 64-bit and 128-bit floating point registers, because of the 32-bit data bus it takes at least 2 clock cycles to fill a 64-bit line. Whereas the U3, being a 64-bit processor, can fetch and execute data in 64-bit blocks at least once per clock cycle (without taking into account any super-scalar processing).<\/p>\n
The P4 has huge instruction set with well over 300 instructions, compared to just under 200 instructions within the U3. Many additional instructions have been added to the P4 instruction set that are focused on dealing with floating point calculations, that would be mostly used in multimedia applications. The U3 has a similar dedicated set of instructions for this purpose, which Sun have named the \u2018Visual Instruction Set\u2019 or VIS. Although the U3 may not have as many instructions to deal with floating point calculations, the U3 has 2 floating point units which can provide simultaneous execution on the floating point instructions, as opposed to the P4\u2019s 1 floating point unit. Although both processors have twin ALU\u2019s, it seems that the U3 generally has many more registers, for example there are 160 general purpose registers compared to the P4\u2019s 8.<\/p>\n
There are scalability issues because the P4 is a uni-processor design, meaning it can only support one processor, whilst the U3 can support multiple processors.<\/p>\n
4.0 \u2013 Cache Design<\/h3>\n
4.1 \u2013 UltraSparc III Cu<\/h4>\n
The UltraSPARC III supports two levels of cache memory. The first level (L1) consists of four separate caches, two large and two small. The second level (L2) consists of a single large cache. The two large L1 caches store instructions and data, respectively. The two smaller L1 caches are: 1.) A pre-fetch cache which stores predicted load instructions. 2.) A write cache, that aims to reduce the amount of storage bandwidth required. All four L1 caches are on-chip. The L2 cache consists of a combined instruction and data cache. The contents of the L2 cache are stored off-chip in Static RAM, but the L2 address tags are kept on-chip for faster access.<\/p>\n
\u00b7\u00a0\u00a0 \u00a0The Instruction cache is 32 KB in size, 32-byte line size (eight instructions) and implements the 4-way set associative mapping function.<\/p>\n
- \n
- The Data cache is 64 KB in size and implements a 4-way set associative mapping function. The data cache uses a write-through policy to replace lines of 32-bytes in size.<\/li>\n
- The Pre-fetch cache is 2 KB in size and implements a 4-way set associative mapping function which uses a write- through policy.<\/li>\n
- The Write cache is 2 KB in size and implements a 4-way set associative mapping function. The line size is 64 bytes with 32-byte sub-blocks and uses a write-back policy.<\/li>\n
- The L2 cache can connect to up to a maximum of 8 MB, implements an 2-way set associative mapping function and uses a write-back policy.<\/li>\n<\/ul>\n
![\"System](\"\/media\/images\/blog\/system-interconnect.jpg\")
<\/p>\nFigure 3. U3 Cache Design. (Courtesy of www.sun.com)<\/p>\n
<\/p>\n
4.2 \u2013 Pentium 4<\/h4>\n
The Pentium 4 also supports 2 levels of cache memory. The first level (L1) consists of two small caches, a Data cache and an Instruction cache. The second level (L2) consists of a single medium size cache. The first small L1 cache is a Data cache and is 8-KB in size has a 4-way set associative mapping function with an 64-byte line size. Interestingly, the capacity has been reduced in size by 50% from the Pentium 3 processor. The second small L1 cache is what Intel refer to as the \u2018Trace Cache\u2019, which is basically a code cache for decoded micro-ops, is 12-KB in size has a 4-way set associative mapping function. Rather than constantly decode the instructions in a loop over and over again, it caches the output of the decoder, caching the raw micro-ops. Both L1 caches implement a write-through page replacement policy.<\/p>\n
The L2 cache holds both data and instructions, is 256-KB in size, has an 8-way set associative mapping function with a 128-byte line size (two 64-byte blocks) and implements a write-back page replacement policy.<\/p>\n
- \n
- The Data cache is 8 KB in size and implements a 4-way set associative mapping function. The data cache uses a write-through policy to replace lines of 64-bytes in size.<\/li>\n
- The Instruction cache (Trace cache) is 12 KB in size and implements the 4-way set associative mapping function, also uses a write-through page replacement policy to replace 32-byte lines.<\/li>\n
- The L2 cache (on chip) is 256 KB in size, has an 8-way set associative mapping function with a 128-byte line size. Implements a write-back page replacement policy.<\/li>\n<\/ul>\n
<\/p>\n
![\"p4](\"\/media\/images\/blog\/p4-cache-design.jpg\")
<\/p>\nFigure 4. P4 Cache Design. (Courtesy of www.hardware.fr)<\/p>\n
<\/p>\n
4.3 \u2013 Comparison<\/h4>\n
4.3.1 \u2013 Overview<\/h5>\n
Both processors employ a multi level cache, utilising a level one and level 2 cache design. At a glance, the most striking difference between the two designs is in the storage capacity, with the UltraSparc having a whooping optimum capacity of 8 MB, opposed to the Pentium 4\u2019s 256 KB. Both designs also have a Data and Instruction cache, but the UltraSparc has the added units of a Write and Pre-fetch cache. At further inspection, it becomes clear how much the two Cache Designs differ.<\/p>\n
4.3.2 \u2013 Level 1 Cache<\/h5>\n
Both processors have a Data cache, the UltraSparcs capacity is larger at 64 KB compared to the Pentium 4\u2019s smaller 8 KB. Also, the Pentium 4 Data cache has 4-way set associative mapping with 64 Byte lines (8 * 64 line block) as opposed to the UltraSparcs 4-way set associative mapping with 32 Byte lines (8 * 32 line block).<\/p>\n
The Pentium \u2018trace cache\u2019 is basically a code cache for decoded micro-ops. Rather than constantly decode the instructions in a loop over and over again, the Pentium 4 caches the output of the decoder in a 12 KB cache. It offers a line size of 32 Bytes and 4-way set associative mapping (4 * 32 Byte Block). The UltraSparc III has an almost identical Instruction cache except for its larger 32 KB capacity. As explained below, the higher Line size does not necessarily result in superior efficiency, on the contrary, hit ratios may be decreased.<\/p>\n
Both L1 Cache designs employ the same write-through policy, which can cause more memory writes and thus prove slower than write-back policy (which only writes when a cache line is rejected) used on both the processors L2 cache design.<\/p>\n
4.3.3 \u2013 Level 2 Cache<\/h5>\n
Quite an obvious advantage of the Pentium’s Cache design is the on-chip L2 cache, which takes advantage of the principle of locality, as opposed to the UltraSparc’s external L2 cache. A fine balance of line size is needed to maximize the hit rate, with this said, the Pentium 4\u2019s L2 cache has 8-way set associative mapping with 128 Byte lines (8 * 128 Byte lines per set or block). Not only is the overall capacity vastly smaller than the UltraSparc, but the block size of 8 lines multiplied by 128 Bytes is quite large and once again, using the principle of locality, may tip the balance of the probability of referencing all the data held in that block, which may ultimately decrease the Pentiums hit ratio.<\/p>\n
5.0 – Pipeline Architecture<\/h3>\n
5.1 \u2013 UltraSparc III Cu<\/h4>\n
To improve performance and in particular clock speed, the Sun Designers have implemented a deep execution pipeline within the UltraSparc III Cu. As a consequence, the design is able to scale up from its initial frequency of 600 MHz to its current frequency of 1050 MHz.<\/p>\n
The processor\u2019s fetch execute cycle has been segmented into 14 separate stages, as can be seen in figure 5, elementary processes such as instruction fetch and store have been fragmented into smaller individual processes, as a consequence, will reduce dead time.<\/p>\n
The UltraSparc employs several separate pipelines, each dedicated to the execution of a particular class of instruction. For example, the execution process (stage 8) of the pipeline can simultaneously execute 4 instructions, possibly to one of the 4 Integer units or one of the two ALU\u2019s (dependant on availability). This design is known as \u2018Super-scalar\u2019, because of the processors ability to issue 4 instructions simultaneously and process them in parallel, it is known as 4-way Super-scalar.<\/p>\n
To reduce the risk of stalling, the processor implements an advanced branch prediction mechanism based on 4 KB\u2019s of stored branch history that accurately predicts whether or not a branch will be taken about 95% of the time[3]. Wrong predictions have a penalty of 7 cycles, required to back up, fetch the branch instruction again, and start over.<\/p>\n
![\"u3](\"\/media\/images\/blog\/u3Pipe.gif\")
<\/p>\nFigure 5. UltraSparc III Cu 14-stage pipeline architecture<\/p>\n
<\/p>\n
<\/p>\n
5.2 \u2013 Pentium 4<\/h4>\n
To increase clock speed, Intel has implemented an extremely deep instruction pipeline, resulting in clock rates of 2GHz and above. The fetch execute cycle has been segmented into 20 separate stages and as can be seen in figure 6, all elementary processes are fragmented except for the store process which is excluded from \u2018Hyper Pipeline\u2019.<\/p>\n
The Pentium 4 pipeline can keep up to 126 instructions ‘in-flight’, amongst them up to 48 load and 24 store operations. The L1 \u2018Trace Cache\u2019 helps reduce the risk of stalling (as detailed in section 4.2).<\/p>\n
An improved branch prediction algorithm has been implemented minimise pipeline flushes. There is also a 4KB branch predictor table, which is eight times larger than that included in the Pentium 3. Intel estimates that the new branch prediction will reduce wrong predictions by one-third.<\/p>\n
Stage\u00a0\u00a0\u00a0 \u00a0\u00a0\u00a0 \u00a0\u00a0\u00a0\u00a0 Pipeline Process:<\/strong>
\n1 – 2\u00a0\u00a0\u00a0 \u00a0\u00a0\u00a0 \u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 Branch prediction supplies address of the next micro-op (TC Nxt IP).
\n3 – 4\u00a0\u00a0\u00a0 \u00a0\u00a0\u00a0 \u00a0\u00a0\u00a0 \u00a0\u00a0\u00a0 Micro-ops are fetched (TC Fetch)\u2026
\n5\u00a0\u00a0\u00a0 \u00a0\u00a0\u00a0 \u00a0\u00a0\u00a0 \u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 and transferred (Drive)\u2026
\n6\u00a0\u00a0\u00a0 \u00a0\u00a0\u00a0 \u00a0\u00a0\u00a0 \u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 into the RAT (register alias table). Allocation of data (Alloc)
\n7 – 8\u00a0\u00a0\u00a0 \u00a0\u00a0\u00a0 \u00a0\u00a0\u00a0 \u00a0 logic registers rename (Rename).
\n9\u00a0\u00a0\u00a0 \u00a0\u00a0\u00a0 \u00a0\u00a0\u00a0 \u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 Micro-ops are put in the Queue until there appears\u2026
\n10 \u2013 11 – 12\u00a0\u00a0\u00a0 free place in the Schedulers.
\n13 – 14\u00a0\u00a0\u00a0 \u00a0\u00a0\u00a0 \u00a0 There, dependencies are to be solved and then micro-ops are transferred to the register files of the\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 corresponding Dispatch Units.
\n15 – 16\u00a0\u00a0\u00a0 \u00a0\u00a0\u00a0 \u00a0 Micro-op is executed, and Flags are calculated.
\n17 – 18\u00a0\u00a0\u00a0 \u00a0\u00a0\u00a0 \u00a0 When implementing the jump instruction\u2026
\n19\u00a0\u00a0\u00a0 \u00a0\u00a0\u00a0 \u00a0\u00a0\u00a0 \u00a0\u00a0\u00a0\u00a0\u00a0 the real branch address and the predicted one are to be compared (Branch Check).
\n20\u00a0\u00a0\u00a0 \u00a0\u00a0\u00a0 \u00a0\u00a0\u00a0 \u00a0\u00a0\u00a0\u00a0\u00a0 After that the new address is recorded in the BTB (Drive).<\/p>\n<\/p>\n
![\"p4](\"\/media\/images\/blog\/p4pipeline.gif\")
<\/p>\nFigure 6. Pentium 4 20-stage pipeline Architecture (Courtesy of www.digit-life.com)<\/p>\n
<\/p>\n
<\/p>\n
5.3 – Comparison<\/h4>\n
The main benefit of a longer pipeline is the ability to process more instructions in fewer clock cycles and it seems Intel have implemented this theory to achieve its higher megahertz ratings. The problem with this design is that the Pentium 4 requires more cycles to complete a given instruction than the shorter UltraSparc pipeline design. Further more, if miss-predictions occur, the whole pipeline needs to be flushed and refilled. The longer the pipeline the more ‘in-flight’ instructions will be lost and the longer it takes until the pipeline is filled again.<\/p>\n
More over, the P4 has a minimum miss-predict penalty of 19 clock cycles for code that’s in the L1 cache as opposed to the UltraSparcs\u2019 7 clock cycle penalty. However, both processors implement a 4KB branch history mechanism that ensures an extremely high percentage of correct branch prediction.<\/p>\n
Another consideration worth mentioning is the fact that the UltraSparc III Cu is a 4-way Super-scalar design, allowing 4 instructions (and at certain stages up to 8) to be processed simultaneously. By comparison, the P4 can process a maximum of 3 instructions per cycle (IPC), limited by its maximum of 3 parallel units.<\/p>\n
One minor flaw in the UltraSparc pipeline architecture was discovered shortly after the release of the chip, Sun Microsystems announced that a design fault in the current UltraSparc III chip had been found that meant a pre-fetch pipeline must be disabled for the chip to correctly handle floating-point calculations[4].<\/p>\n
<\/p>\n
6.0 \u2013 Conclusion<\/h3>\n
The Intel Pentium family of processors have enjoyed widespread use in the majority of home PC\u2019s, with the ever increasing demand and use of multimedia applications in the home and the fact that high clock speeds sell, the Pentium 4 processor has been designed with these goals in mind. The UltraSparc III Cu on the other hand, is commonly found in an enterprise network computing environment. The UltraSparc III is essentially designed to work in systems ranging from single processor workstations through to cache coherent servers with over a hundred processors. Not only that, but Sun Microsystems specifically direct their hardware and thus the UltraSparc III processors towards the business market.<\/p>\n
The Pentium 4 offers extremely high clock rates, which have been achieved by primarily redesigning and increasing the pipeline depth. The 20-stage pipeline does not come without its drawbacks, especially if the pipeline is not provided with a constant stream of instructions. Other additions include an increased instruction set (SSE2) aimed at multimedia specific computation such as 3D pixel rendering. The introduction of a \u2018Trace Cache\u2019 which has resulted in a decrease in the P4 L1 cache to only 8 KB (half the size of its predecessor), but as a trade off, Intel was probably forced to reduce the size of the L1 data cache to enable its extremely low latency of only 2 clock cycles.<\/p>\n
The UltraSparc III Cu processor is a high-performance, super-scalar processor that implements the 64-bit SPARC-V9 RISC architecture. It can sustain the execution of up to four instructions per cycle, even under conditional branches and cache misses, mainly because the units are asynchronously supplied instructions and data to the rest of the pipeline. As with the P4, the U3 has an increased instruction set (VIS) aimed at multimedia specific computation, although not achieving as impressive clock rates as the P4, the U3 has the benefit of\u00a0 being 4-way super-scalar.<\/p>\n
In essence, both processors have been designed to work within completely different environments, although from a marketing point of view, both processors have to be seen to deal with any computing situation. A particular task initiated on one processor may out perform the other and vice versa, essentially it\u2019s a matter of using a specific processor for a certain type of application to gain the best results.<\/p>\n
<\/p>\n
<\/p>\n
Appendix A \u2013 Performance Benchmarks<\/h3>\n
The following benchmarks are taken from the SPEC\u00aecpu system and are probably the most frequently referenced benchmarks in the computing industry. It is a suite of tests that is developed by the Standard Performance Evaluation Corporation (SPEC, http:\/\/www.spec.org). The suite is based on real applications and is divided into two categories; Integer\u00a0 (MIPS) and Floating point (GFLOPS).<\/p>\n
Integer (SPECint\u00ae2000)<\/h4>\n
![\"benchmark](\"\/media\/images\/blog\/benchInt.gif\")
<\/p>\nFloating point (SPECfp\u00ae2000)<\/h4>\n
![\"benchmark](\"\/media\/images\/blog\/benchFp.gif\")
<\/p>\n<\/p>\n
Pentium 4 Integer Results<\/h4>\n
![\"benckmark](\"\/media\/images\/blog\/p4Int.gif\")
<\/p>\nUltraSparc III Cu Integer Results<\/h4>\n
<\/p>\n
![\"benckmark](\"\/media\/images\/blog\/u3Int.gif\")
<\/p>\nPentium 4 Floating-Point Results<\/h4>\n
![\"benckmark](\"\/media\/images\/blog\/p4Fp.gif\")
<\/p>\nUltraSparc III Cu Floating-Point Results<\/h4>\n
![\"benckmark](\"\/media\/images\/blog\/uSFp.gif\")
<\/p>\n<\/p>\n
Appendix B \u2013 Block Diagrams<\/h3>\n
UltraSparc III Cu Basic Block Diagram<\/h4>\n
![\"u3](\"\/media\/images\/blog\/u3Block.jpg\")
<\/p>\nPentium 4 Basic Block Diagram.<\/h4>\n
![\"p4](\"\/media\/images\/blog\/p4Block.gif\")
<\/p>\n<\/p>\n
<\/p>\n
Appendix C \u2013 Glossary of Acronyms<\/h3>\n
ALU\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 Arithmetic Logic Unit
\nCISC\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 Complex Instruction Set Computer
\nCPU\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 Central Processing Unit
\nCU\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 Control Unit
\nDRAM\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 Dynamic Random Access Memory
\nFP\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 Floating Point
\nGFLOPS\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 Giga FLoating point Operations Per Second
\nGHz\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 Giga Hertz
\nIA \u2013 32\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 Intels\u2019 32-bit Instruction set Architecture
\nILP\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 Instruction Level Parallelism
\nIPC\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 Instructions Per Cycle
\nISA\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 Instruction Set Architecture
\nKB\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 Kilobyte
\nL1\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 Level one cache
\nL2\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 Level two cache
\nMFLOPS\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 Mega FLoating point Operations Per Second
\nMHz\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 Mega Hertz
\nMIPS\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 Millions of Instructions Per Second
\nMB\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 Megabyte
\nRAM\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 Random Access Memory
\nRISC\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 Reduced Instruction Set Computer
\nSDRAM\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 Synchronous Dynamic Random Access Memory
\nSIMD\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 Single Instruction stream-Multiple Data stream
\nSSE2\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 Streaming SIMD Extension 2
\nSPARC\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 Scalable Processor ARCitecture
\nSRAM\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 Static Random Access Memory
\nVIS\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 Visual Instruction Set<\/p>\n<\/p>\n
<\/p>\n
Bibliography<\/h3>\n
Books<\/h4>\n
Computer Architecture design and performance \u2013 B. Wilkinson, Prentice Hall 1996
\nComputer Organisation and Architecture \u2013 B.S. Chalk, Macmillan 1996.
\nHigh-Performance Computer Architecture \u2013 H.S. Stone, Addison-Wesley 1993<\/p>\nWWW<\/h4>\n
http:\/\/www.intel.com
\nhttp:\/\/www.intel.com\/design\/Pentium4\/prodbref\/
\nhttp:\/\/intel.com\/technology\/itj\/q12001\/articles\/art_2.htm
\nhttp:\/\/www.sun.com
\nhttp:\/\/www.sun.com\/processors\/UltraSPARC-III\/
\nhttp:\/\/www.sun.com\/processors\/whitepapers\/index.html#III
\nhttp:\/\/www.sun.com\/processors\/UltraSPARC-III\/USIIICuoverview.pdf
\nhttp:\/\/www.sparc.org
\nhttp:\/\/www.anandtech.com\/showdoc.html?i=1360&p=15
\nhttp:\/\/www.emulators.com\/pentium4.htm
\nhttp:\/\/web.archive.org\/web\/20030519220247\/http:\/\/meseec.ce.rit.edu:80\/eecc550-spring2002\/550-3-20-2002.pdf
\nhttp:\/\/www.arstechnica.com\/cpu\/01q2\/p4andg4e\/p4andg4e-1.html
\nhttp:\/\/www.aceshardware.com\/Spades\/read.php?article_id=20000190
\nhttp:\/\/www.emulators.com\/pentium4.htm
\nhttp:\/\/www.netsoc.tcd.ie\/~nickm\/4ba2\/performance\/mythicalmegahertz.pdf
\nhttp:\/\/www.chipcenter.com\/eexpert\/dgilbert\/dgilbert074.html
\nhttp:\/\/www.dell.com\/us\/en\/gen\/topics\/vectors_2001-pentium4performance.htm
\nhttp:\/\/sysopt.earthweb.com\/articles\/usparc-3\/index6.html
\nhttp:\/\/web.archive.org\/web\/20080911155138\/http:\/\/www.eng.dmu.ac.uk:80\/~pdn\/UltraSPARC\/ultra_arch_architecture.html
\nhttp:\/\/web.archive.org\/web\/20031206201454\/http:\/\/www.ee.princeton.edu:80\/~xzhu\/p4.html
\nhttp:\/\/www6.tomshardware.com\/cpu\/00q4\/001120\/p4-05.html
\nhttp:\/\/www.cs.berkeley.edu\/~pattrsn\/61CF00\/lectures\/lec23-x86.pdf
\nhttp:\/\/www.euro.dell.com\/countries\/eu\/enu\/gen\/topics\/vectors_2000-pentium4.htm
\nhttp:\/\/www.owlnet.rice.edu\/~elec525\/lectures\/lecture02.pdf
\nhttps:\/\/web.archive.org\/web\/20081121160923\/http:\/\/www.digit-life.com\/articles\/pentium4\/index2.html<\/p>\n<\/p>\n","protected":false},"excerpt":{"rendered":"
The following report consists of a critical architectural comparison of the UltraSparc III Cu and Pentium 4 processors. Research will be undertaken and the findings will be presented in a format of various sections, each offering a detailed view of relevant aspects of the processors’ design followed by a brief comparison between the two.<\/p>\n","protected":false},"author":4,"featured_media":0,"comment_status":"open","ping_status":"closed","sticky":false,"template":"","format":"standard","meta":{"footnotes":""},"categories":[8],"tags":[],"class_list":["post-73","post","type-post","status-publish","format-standard","hentry","category-papers"],"yoast_head":"\n
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